Motorola DSP56301 Manual de usuario

DSP56301 User’s Manual24-Bit Digital Signal ProcessorDSP56301UM/ADRevision 3, March 2001

x DSP56303 DSP56301 User’s ManualChapter 9 Triple Timer Module9.1 Overview...

Bus Interface Unit (BIU) Registers4-26 DSP56301 User’s Manual11 BPLE 0 Bus Page Logic EnableEnables/disables the in-page identifying logic. When BPLE

Bus Interface Unit (BIU) RegistersCore Configuration 4-274.6.3 Address Attribute Registers (AAR[0–3])The Address Attribute Registers (AAR[0–3]) are re

Bus Interface Unit (BIU) Registers4-28 DSP56301 User’s Manual7 BPAC 0 Bus Packing EnableEnables/disables the internal packing/unpacking logic. When BP

DMA Control Registers 5–0 (DCR[5–0])Core Configuration 4-294.7 DMA Control Registers 5–0 (DCR[5–0])The DMA Control Registers (DCR[5–0]) are read/write

DMA Control Registers 5–0 (DCR[5–0])4-30 DSP56301 User’s Manual22 DIE 0 DMA Interrupt EnableGenerates a DMA interrupt at the end of a DMA block transf

DMA Control Registers 5–0 (DCR[5–0])Core Configuration 4-3118–17 DPR[1–0] 0 DMA Channel PriorityDefine the DMA channel priority relative to the other

DMA Control Registers 5–0 (DCR[5–0])4-32 DSP56301 User’s Manual18–17 cont.DPR[1–0]OMR - CDP[1–0] CP[1–0] Core Priority00 00 0 (lowest)00 01 100 10 200

DMA Control Registers 5–0 (DCR[5–0])Core Configuration 4-3315–11 DRS[4–0] 0 DMA Request SourceEncodes the source of DMA requests that trigger the DMA

Device Identification Register (IDR)4-34 DSP56301 User’s Manual4.8 Device Identification Register (IDR)The IDR is a read-only factory-programmed regis

JTAG Identification (ID) RegisterCore Configuration 4-354.9 JTAG Identification (ID) RegisterThe JTAG ID register is a 32-bit read-only factory-progra

DSP56301 User’s Manual xiFigures1-1 DSP56301 Block Diagram ... 1-112-1

JTAG Boundary Scan Register (BSR)4-36 DSP56301 User’s Manual

Programming the Peripherals 5-1Chapter 5Programming the PeripheralsWhen the DSP56301 peripherals (HI32, ESSI, SCI, and Timers) are programmed in a giv

Mapping the Control Registers5-2 DSP56301 User’s Manual5.2 Mapping the Control RegistersThe I/O peripherals are controlled through registers mapped to

Data Transfer MethodsProgramming the Peripherals 5-3DSP56300 core does not execute any other code. Polling is the easiest transfer method since it doe

General-Purpose Input/Output (GPIO)5-4 DSP56301 User’s Manual5.3.3 DMAThe Direct Memory Access (DMA) controller permits data transfers between interna

General-Purpose Input/Output (GPIO)Programming the Peripherals 5-55.4.1 Port B Signals and RegistersAs shown in Figure 5-2, you can configure twenty-f

General-Purpose Input/Output (GPIO)5-6 DSP56301 User’s Manual5.4.2 Port C Signals and RegistersEach of the six Port C signals not used as an ESSI0 sig

General-Purpose Input/Output (GPIO)Programming the Peripherals 5-75.4.5 Triple Timer Signals and RegistersEach of the three triple timer interface sig

General-Purpose Input/Output (GPIO)5-8 DSP56301 User’s Manual

Host Interface (HI32) 6-1Chapter 6Host Interface (HI32)The Host Interface (HI32) is a fast parallel host port up to 32 bits wide that can directly con

xii DSP56301 User’s Manual6-8 DSP PCI Address Register (DPAR)... 6-336-9 DSP Status

Features6-2 DSP56301 User’s ManualTable 6-1. HI32 Features, Core-Side and Host-SideFeature Core-Side Interface Host-Side InterfaceMapping 11 internal

FeaturesHost Interface (HI32) 6-3Handshaking Protocolsn Software polledn Interrupt driven (fast or long)n Direct Memory Access (up to six DSP56300 cor

Overview6-4 DSP56301 User’s Manual6.2 OverviewFigure 6-1 shows the two banks of registers in the HI32, DSP-side and host-side. The DSP56300 core can a

OverviewHost Interface (HI32) 6-5Figure 6-1. HI32 Block DiagramIn Self-Configuration mode (DCTR[HM] = $5), the DSP56300 core can indirectly write al

Data Transfer Paths6-6 DSP56301 User’s ManualDMA controllers, or standard peripheral buses (for example, ISA/EISA) because the interface appears to th

Data Transfer PathsHost Interface (HI32) 6-7In PCI mode data transfers in which the HI32 is the target (DCTR[HM] = $1) with HCTR[HTF]≠$0, the host-t

Data Transfer Paths6-8 DSP56301 User’s ManualHRXS. Each time the host reads a 32-bit word from the HRXS, the 32-bits of significant data located in tw

Data Transfer PathsHost Interface (HI32) 6-91 1 The three least significant HRXM bytes are output left aligned and zero filled.The three most signific

Data Transfer Paths6-10 DSP56301 User’s Manual1 0 The three least significant PCI data bytes are written to the HTXR.HD[15–0] are written to the HTXR,

Data Transfer PathsHost Interface (HI32) 6-110 1 The three least significant HRXS bytes are output right aligned and zero extended.The two least signi

DSP56301 User’s Manual xiii8-4 SCI Clock Control Register (SCCR)... 8-198-5 SCI Baud

Reset States6-12 DSP56301 User’s Manual6.4 Reset StatesTable 6-6 describes the various HI32 reset states.6.5 DSP-Side Operating ModesThe HI32 Mode (DC

DSP-Side Operating ModesHost Interface (HI32) 6-136.5.1 Terminate and Reset (DCTR[HM] = $0)When DCTR[HM2–0] is written with a value of $0 and the HI

DSP-Side Operating Modes6-14 DSP56301 User’s ManualExample 6-1. PCI /DMA Throughput (32-Bit)PCI clock = 33 MHz56301 core clock = 66 MHz33-

DSP-Side Operating ModesHost Interface (HI32) 6-15(pci_cyc + pci_w.s) x multfactor = tot_cyc 1 + 0 x 2 = 2multfactor = 2 b

DSP-Side Operating Modes6-16 DSP56301 User’s ManualIn addition, for Universal Bus mode, pins HP[22–20] are GPI/O. For Enhanced Universal Bus mode, two

DSP-Side Operating ModesHost Interface (HI32) 6-17never changed. Therefore the upper 16 bits of the base address are written to every register locati

Host Port Pins6-18 DSP56301 User’s Manual6.6 Host Port PinsThe HI32 signals are discussed in Chapter 2. In this section, Table 6-8 summarizes the pin

Host Port PinsHost Interface (HI32) 6-19Figure 6-2. Connection to a PCI BusAD[31–0]C3/BE3–C0/BE0FRAMEIRDYTRDYSTOPPARDEVSELPERRSERRREQGNTIDSELRSTCLKHAD

Host Port Pins6-20 DSP56301 User’s ManualFigure 6-3. Connection to 16-Bit ISA/EISA Data BusHDBENHDBDRBUFHA10HAENHD[15–0]HTAHWRHRDHSAKHIRQHDRQHDAKDSP56

Host Port PinsHost Interface (HI32) 6-21Figure 6-4. Connection to the DSP56300 Core Port A BusD[23–0]A[10–0]TAWRRDAA0IRQAHA[10–0]HAENHD[23–0]HTAHWRHRD

xiv DSP56301 User’s ManualB-9 DMA Control Registers 5–0 (DCR[5–0])...B-21B-10 DSP Control Reg

HI32 DSP-Side Programming Model6-22 DSP56301 User’s Manual6.7 HI32 DSP-Side Programming ModelThe DSP56300 core views the HI32 as a memory-mapped perip

HI32 DSP-Side Programming ModelHost Interface (HI32) 6-236.7.1 DSP Control Register (DCTR)The DCTR is a 24-bit read/write control register by which th

HI32 DSP-Side Programming Model6-24 DSP56301 User’s Manual19 HIRD 0 UB Host Interrupt Request Drive ControlControls the output drive of the HIRQ pin w

HI32 DSP-Side Programming ModelHost Interface (HI32) 6-2515 HTAP 0 UB Host Transfer Acknowledge PolarityControls the polarity of the HTA pin when the

HI32 DSP-Side Programming Model6-26 DSP56301 User’s Manual6.7.2 DSP PCI Control Register (DPCR)The DPCR is a 24-bit read/write control register by whi

HI32 DSP-Side Programming ModelHost Interface (HI32) 6-27Table 6-11. DSP PCI Control Register (DPCR) Bit DefinitionsBit Number Bit Name Reset Value De

HI32 DSP-Side Programming Model6-28 DSP56301 User’s Manual19 MWSD 0 Master Wait State DisableDisables PCI wait states (inserted by deasserting HIRDY)

HI32 DSP-Side Programming ModelHost Interface (HI32) 6-2914 CLRT 0 Clear TransmitterClears the HI32 master-to-host bus data path in PCI mode (DCTR[HM]

HI32 DSP-Side Programming Model6-30 DSP56301 User’s Manual6.7.3 DSP PCI Master Control Register (DPMC)The DPMC is a 24-bit read/write register by whic

HI32 DSP-Side Programming ModelHost Interface (HI32) 6-31Table 6-12. DSP PCI Master Control Register (DMPC) Bit DefinitionsBit Number Bit Name Reset V

Tables xvTables1-1 High True/Low True Signal Conventions ... 1-21-2 DSP56301 Switch Memo

HI32 DSP-Side Programming Model6-32 DSP56301 User’s Manual23–22Cont.FC[1–0]Cont.0 DPMC[FC] = $1 or $2 The three least significant PCI data bytes from

HI32 DSP-Side Programming ModelHost Interface (HI32) 6-336.7.4 DSP PCI Address Register (DPAR)A 24-bit read/write register by which the DSP56300 core

HI32 DSP-Side Programming Model6-34 DSP56301 User’s Manual19–16 C[3–0] 0 PCI Bus CommandDefines the PCI bus command. When the DSP56300 core writes to

HI32 DSP-Side Programming ModelHost Interface (HI32) 6-356.7.5 DSP Status Register (DSR).A 24-bit read-only status register by which the DSP56300 core

HI32 DSP-Side Programming Model6-36 DSP56301 User’s Manual5–3 HF[2–0] 0 UBMPCIHost FlagsIndicate the state of host flags HF[2–0], respectively, in the

HI32 DSP-Side Programming ModelHost Interface (HI32) 6-371STRQ 1 UBMPCISlave Transmit Data RequestIndicates that the slave transmit data FIFO (DTXS) i

HI32 DSP-Side Programming Model6-38 DSP56301 User’s Manual6.7.6 DSP PCI Status Register (DPSR) .A 24-bit read-only status register by which the DSP563

HI32 DSP-Side Programming ModelHost Interface (HI32) 6-3914 MDT 0 Master Data TransferredIndicates the status of the latest completed PCI transaction

HI32 DSP-Side Programming Model6-40 DSP56301 User’s Manual9TDIS0PCI Target DisconnectIndicates that an HI32-initiated PCI transaction has terminated w

HI32 DSP-Side Programming ModelHost Interface (HI32) 6-416.7.7 DSP Receive Data FIFO (DRXR)The 24-bit wide DSP Receive Data Register (DRXR) is the out

xvi DSP56301 User’s Manual6-10 DSP Control Register (DCTR) Bit Definitions ... 6-236-11 DSP PCI Co

HI32 DSP-Side Programming Model6-42 DSP56301 User’s Manualwhen the host-to-DSP data path FIFO is emptied by DSP56300 core reads. The DSP56300 core can

HI32 DSP-Side Programming ModelHost Interface (HI32) 6-436.7.10 DSP Host Port GPIO Direction Register (DIRH) A 24-bit read/write register by which the

Host-Side Programming Model6-44 DSP56301 User’s Manual6.8 Host-Side Programming ModelThe HI32 appears to the host processor as a bank of registers, li

Host-Side Programming ModelHost Interface (HI32) 6-45hardware can be used with the handshake flags to transfer data without host processor interventio

Host-Side Programming Model6-46 DSP56301 User’s Manualn The HI32 does not reach deadlock due to illegal PCI events. Illegal PCI events bring the HI32

Host-Side Programming ModelHost Interface (HI32) 6-47 Table 6-19. Host-Side Registers (PCI Memory Address Space1)Base Address: $0000Base Address:$000C

Host-Side Programming Model6-48 DSP56301 User’s Manual6.8.1 HI32 Control Register (HCTR)The HCTR is a 32-bit read/write control register by which the

Host-Side Programming ModelHost Interface (HI32) 6-49Table 6-22. Host Interface Control Register (HCTR) Bit DefinitionsBit NumberBit NameReset ValueMo

Host-Side Programming Model6-50 DSP56301 User’s Manual13 0 Reserved. Write to zero for future compatibility.12–11 HRF[1–0] 0UBMPCIHost Receive Data Tr

Host-Side Programming ModelHost Interface (HI32) 6-519–8 HTF[1–0] 0UBMPCIHost Transmit Data Transfer FormatDefine data transfer formats for host-to-DS

Overview 1-1Chapter 1OverviewThis manual describes the DSP56301 24-bit digital signal processor (DSP), its memory, operating modes, and peripheral mod

Host-Side Programming Model6-52 DSP56301 User’s Manual9–8 cont.HTF[1–0] 0UBMPCIHost Transmit Data Transfer Format (cont.)Note: When the HI32 is in PCI

Host-Side Programming ModelHost Interface (HI32) 6-537 Cont. SFT Cont. 0UBMPCIUniversal Bus mode (DCTR[HM] = $2 or $3)Fetch (SFT = 1): There is no FI

Host-Side Programming Model6-54 DSP56301 User’s Manual6DMAE0UBMDMA Enable (ISA/EISA)Used by the host processor to enable the HI32 ISA/EISA DMA-type ac

Host-Side Programming ModelHost Interface (HI32) 6-552 RREQ 0UBMReceive Request EnableControls the HIRQ and HDRQ pins for DSP-to-host data transfers i

Host-Side Programming Model6-56 DSP56301 User’s Manual6.8.2 Host Interface Status Register (HSTR)The HSTR is a 32-bit read-only status register by whi

Host-Side Programming ModelHost Interface (HI32) 6-57n In a 16-bit data Universal Bus mode (DCTR[HM] = $2 or $3 and HCTR[HRF]≠$0), the HD[15–0] pins a

Host-Side Programming Model6-58 DSP56301 User’s Manual2 HRRQ 0 UBMPCIHost Receive Data RequestIndicates that the host slave receive data FIFO (HRXS) c

Host-Side Programming ModelHost Interface (HI32) 6-596.8.3 Host Command Vector Register (HCVR))The HCVR is a 32-bit read/write register by which the h

Host-Side Programming Model6-60 DSP56301 User’s ManualIf TWSD is cleared, the HI32 is the selected PCI target (DCTR[HM] = $1) in a write data phase to

Host-Side Programming ModelHost Interface (HI32) 6-616.8.4 Host Master Receive Data Register (HRXM)The HRXM is the output stage of the master DSP-to-h

Manual Conventions1-2 DSP56301 User’s Manualn Chapter 6, Host Interface (HI32) HI32 features, signals, architecture, programming model, reset, interr

Host-Side Programming Model6-62 DSP56301 User’s Manualthe pins and their alignment. (See Section 6.3.2, DSP-To-Host Data Path, on page 6-7 and Sectio

Host-Side Programming ModelHost Interface (HI32) 6-63The HTXR receives data from the HI32 data pins via the data transfer format converter (HDTFC). Th

Host-Side Programming Model6-64 DSP56301 User’s Manual6.8.7 Device ID/Vendor ID Configuration Register (CDID/CVID)r A PCI-standard 32-bit read-only re

Host-Side Programming ModelHost Interface (HI32) 6-65read/write command is in progress and the PCI address is $04. In Self-Configuration mode (DCTR[DC

Host-Side Programming Model6-66 DSP56301 User’s Manual23 FBBC 0 Fast Back-to-Back Capable (hardwired to one)Indicates that the HI32 supports fast back

Host-Side Programming ModelHost Interface (HI32) 6-676.8.9 Class Code/Revision ID Configuration Register (CCCR/CRID)r (A PCI-standard 32-bit read-only

Host-Side Programming Model6-68 DSP56301 User’s Manual6.8.10 Header Type/Latency Timer Configuration Register (CHTY/CLAT/CCLS)r (A PCI-standard read/w

Host-Side Programming ModelHost Interface (HI32) 6-6915–8 LT[7–0] 0 Latency Timer (High)In PCI mode (HM = $1), specify the value of the latency timer

Host-Side Programming Model6-70 DSP56301 User’s Manual6.8.11 Memory Space Base Address Configuration Register (CBMA)r A PCI-standard read/write regist

Host-Side Programming ModelHost Interface (HI32) 6-716.8.12 Subsystem ID and Subsystem Vendor ID Configuration Register (CSID)r A PCI-standard read/wr

Manual ConventionsOverview 1-3n Pins or signals that are asserted low (made active when pulled to ground) are indicated like this:— In text, they have

Host-Side Programming Model6-72 DSP56301 User’s ManualUse the following procedure for writing to the CSID:1. Power up the DSP56301.The default CSID va

Host-Side Programming ModelHost Interface (HI32) 6-736.8.13 Interrupt Line-Interrupt Pin Configuration Register(CILP) CILP is PCI-standard read-only r

HI32 Programming Model/Quick Reference6-74 DSP56301 User’s Manual6.9 HI32 Programming Model/Quick ReferenceHI32 Registers—Quick ReferenceRegBitComment

HI32 Programming Model/Quick ReferenceHost Interface (HI32) 6-75DCTRcont.22-20HM[2–0] HI32 Mode 00000101001110010111xTerminate and ResetPCIUBMEnhance

HI32 Programming Model/Quick Reference6-76 DSP56301 User’s ManualDPMC15-0AR[31–16] DSP PCI Transaction Address (High)written only if MARQ = 1$0000 - -

HI32 Programming Model/Quick ReferenceHost Interface (HI32) 6-77DPSRcont.5APER PCI Address Parity Error01HI32 target has not detected an address parit

HI32 Programming Model/Quick Reference6-78 DSP56301 User’s ManualHost SideHCTR1TREQ Transmit Request Enable01HTRQ interrupt disabledHTRQ interrupt ena

HI32 Programming Model/Quick ReferenceHost Interface (HI32) 6-79HCVR0HC Host Command 01no host command pendinghost command pendingcleared when the HC

HI32 Programming Model/Quick Reference6-80 DSP56301 User’s ManualCCMRCSTRcont.29RMA Received Master Abort 01HI32 has not received a master-abort event

Enhanced Synchronous Serial Interface (ESSI) 7-1Chapter 7Enhanced Synchronous Serial Interface (ESSI)The ESSI provides a full-duplex serial port for s

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty,representation or guarantee rega

DSP56300 Core Features1-4 DSP56301 User’s Manual1.3 DSP56300 Core FeaturesAll DSP56300 core family members contain the DSP56300 core and additional mo

ESSI Enhancements7-2 DSP56301 User’s ManualNote: This synchronous interface should not be confused with the asynchronous channels mode of the ESSI, in

ESSI Data and Control SignalsEnhanced Synchronous Serial Interface (ESSI) 7-37.2 ESSI Data and Control SignalsThree to six signals are required for ES

ESSI Data and Control Signals7-4 DSP56301 User’s Manual7.2.4 Serial Control Signal (SC0)ESSI0: SC00; ESSI1: SC10To determine the function of the SC0 s

ESSI Data and Control SignalsEnhanced Synchronous Serial Interface (ESSI) 7-5When configured as an output, SC1 functions as a serial Output Flag, as t

Operation7-6 DSP56301 User’s Manual7.2.6 Serial Control Signal (SC2)ESSI0:SC02; ESSI1:SC12SC2 is a frame sync I/O signal for both the transmitter and

OperationEnhanced Synchronous Serial Interface (ESSI) 7-7ESSI, use an ESSI individual reset when you change the ESSI control registers (except for bit

Operation7-8 DSP56301 User’s Manualn ESSI receive last slot interrupt:Occurs when the ESSI is in Network mode and the last slot of the frame has ended

OperationEnhanced Synchronous Serial Interface (ESSI) 7-9To configure an ESSI exception, perform the following steps:1. Configure the interrupt servic

Operating Modes: Normal, Network, and On-Demand7-10 DSP56301 User’s Manual7.4 Operating Modes: Normal, Network, and On-DemandThe ESSI has three basic

Operating Modes: Normal, Network, and On-DemandEnhanced Synchronous Serial Interface (ESSI) 7-117.4.2 Synchronous/Asynchronous Operating ModesThe tran

DSP56300 Core FeaturesOverview 1-5n Phase Lock Loop (PLL)—Allows change of low power Divide Factor (DF) without loss of lockn Output clock with skew e

Operating Modes: Normal, Network, and On-Demand7-12 DSP56301 User’s Manual7.4.5 Frame Sync Length for Multiple DevicesThe ability to mix frame sync le

Operating Modes: Normal, Network, and On-DemandEnhanced Synchronous Serial Interface (ESSI) 7-137.4.8 Byte Format (LSB/MSB) for the TransmitterSome de

ESSI Programming Model7-14 DSP56301 User’s Manual7.5 ESSI Programming ModelThe ESSI is composed of the following registers:n Two control registers (CR

ESSI Programming ModelEnhanced Synchronous Serial Interface (ESSI) 7-15Table 7-3. ESSI Control Register A (CRA) Bit DefinitionsBit Number Bit Name Res

ESSI Programming Model7-16 DSP56301 User’s Manual18 ALC 0 Alignment ControlThe ESSI handles 24-bit fractional data. Shorter data words are left-aligne

ESSI Programming ModelEnhanced Synchronous Serial Interface (ESSI) 7-17Figure 7-3. ESSI Clock Generator Functional Block DiagramFigure 7-4. ESSI Frame

ESSI Programming Model7-18 DSP56301 User’s Manual7.5.2 ESSI Control Register B (CRB)CRB is one of two read/write control registers that direct the ope

ESSI Programming ModelEnhanced Synchronous Serial Interface (ESSI) 7-19Enable (TEIE) bits. In Network mode, if you clear the appropriate TE bit and se

ESSI Programming Model7-20 DSP56301 User’s Manual18 TIE 0 Transmit Interrupt EnableEnables/disables a DSP transmit interrupt; the interrupt is generat

ESSI Programming ModelEnhanced Synchronous Serial Interface (ESSI) 7-2115 TE1 0 Transmit 1 EnableEnables the transfer of data from TX1 to Transmit Shi

DSP56300 Core Functional Blocks1-6 DSP56301 User’s Manual— Serial Communications Interface (SCI) with baud rate generator— Triple timer module— Up to

ESSI Programming Model7-22 DSP56301 User’s Manual11 CKP 0 Clock Polarity Controls which bit clock edge data and frame sync are clocked out and latched

ESSI Programming ModelEnhanced Synchronous Serial Interface (ESSI) 7-234 SCD2 0 Serial Control Direction 2Controls the direction of the SC2 I/O signal

ESSI Programming Model7-24 DSP56301 User’s ManualFigure 7-6. CRB FSL0 and FSL1 Bit Operation (FSR = 0) Serial ClockRX, TX Frame SYNCWord Length: FSL1

ESSI Programming ModelEnhanced Synchronous Serial Interface (ESSI) 7-25Figure 7-7. CRB SYN Bit OperationExternal Frame SYNCSC1Asynchronous (SYN = 0)Tr

ESSI Programming Model7-26 DSP56301 User’s ManualFigure 7-8. CRB MOD Bit OperationSSI Control Register B (CRB) (READ/WRITE)Normal Mode (MOD = 0)Serial

ESSI Programming ModelEnhanced Synchronous Serial Interface (ESSI) 7-27Figure 7-9. Normal Mode, External Frame Sync (8 Bit, 1 Word in Frame)Figure 7-1

ESSI Programming Model7-28 DSP56301 User’s Manual7.5.3 ESSI Status Register (SSISR)The SSISR is a read-only status register by which the DSP reads the

ESSI Programming ModelEnhanced Synchronous Serial Interface (ESSI) 7-297.5.4 ESSI Receive Shift RegisterThe 24-bit Receive Shift Register (see Figure

ESSI Programming Model7-30 DSP56301 User’s Manual7.5.5 ESSI Receive Data Register (RX)The Receive Data Register (RX) is a 24-bit read-only register th

ESSI Programming ModelEnhanced Synchronous Serial Interface (ESSI) 7-31Figure 7-12. ESSI Data Path Programming Model (SHFD = 0)SRDESSI Receive Data Re

DSP56300 Core Functional BlocksOverview 1-71.4.1.1 Data ALU RegistersThe data ALU registers are read or written over the X data bus and the Y data bus

ESSI Programming Model7-32 DSP56301 User’s ManualFigure 7-13. ESSI Data Path Programming Model (SHFD = 1)SRDESSI Receive Data Register (Read Only)ESSI

ESSI Programming ModelEnhanced Synchronous Serial Interface (ESSI) 7-337.5.7 ESSI Transmit Data Registers (TX[2–0])ESSI0:TX20, TX10, TX00; ESSI1:TX21,

ESSI Programming Model7-34 DSP56301 User’s ManualTSMA and TSMB (as in Figure 7-12 and Figure 7-13) can be seen as a single 32-bit register, TSM. Bit n

ESSI Programming ModelEnhanced Synchronous Serial Interface (ESSI) 7-357.5.10 Receive Slot Mask Registers (RSMA, RSMB)Both receive slot mask registers

GPIO Signals and Registers7-36 DSP56301 User’s Manual7.6 GPIO Signals and RegistersThe functionality of each ESSI port is controlled by three register

GPIO Signals and RegistersEnhanced Synchronous Serial Interface (ESSI) 7-377.6.2 Port Direction Registers (PRRC and PRRD)The read/write PRRC and PRRD

GPIO Signals and Registers7-38 DSP56301 User’s Manual7.6.3 Port Data Registers (PDRC and PDRD)Bits 5–0 of the read/write PDRs write data to or read da

Serial Communication Interface (SCI) 8-1Chapter 8Serial Communication Interface (SCI)The DSP56301 Serial Communication Interface (SCI) provides a full

Operating Modes8-2 DSP56301 User’s Manualtransmit and receive clock compatible with the Intel 8051 serial interface mode 0 synchronizes data. Asynchro

I/O SignalsSerial Communication Interface (SCI) 8-3message and optionally transmit an acknowledgment to the sender. The particular message format and

DSP56300 Core Functional Blocks1-8 DSP56301 User’s Manualarithmetic used in the address register update calculation. The modifier value is decoded in

I/O Signals8-4 DSP56301 User’s ManualHowever, at least one of the three signals must be selected as an SCI signal to release the SCI from reset.To ena

SCI After ResetSerial Communication Interface (SCI) 8-58.3 SCI After ResetThere are several different ways to reset the SCI:n Hardware RESET signaln S

SCI Initialization8-6 DSP56301 User’s Manual8.4 SCI InitializationThe SCI is initialized as follows:1. Ensure that the SCI is in its individual reset

SCI InitializationSerial Communication Interface (SCI) 8-7There are two workarounds for this issue:n Enable an SCI pin other than SCLK.n In the next i

Exceptions8-8 DSP56301 User’s ManualAfter the current character transmission, if two or more of these commands are set, the transmitter executes them

SCI Programming ModelSerial Communication Interface (SCI) 8-94. SCI idle line occurs when the receive line enters the idle state (10 or 11 bits of one

SCI Programming Model8-10 DSP56301 User’s ManualFigure 8-1. SCI Data Word Formats (SSFTD = 1), 1Mode 08-bit Synchronous Data (Shift Register Mode)TX(S

SCI Programming ModelSerial Communication Interface (SCI) 8-11Figure 8-2. SCI Data Word Formats (SSFTD = 0), 2Mode 08-bit Synchronous Data (Shift Regi

SCI Programming Model8-12 DSP56301 User’s Manual8.6.1 SCI Control Register (SCR)The SCR is a read/write register that controls the serial interface op

SCI Programming ModelSerial Communication Interface (SCI) 8-1313 TMIE 0 Timer Interrupt EnableEnables/disables the SCI timer interrupt. If TMIE is set

DSP56300 Core Functional BlocksOverview 1-91.4.4 PLL and Clock Oscillator The clock generator in the DSP56300 core comprises two main blocks: the PLL,

SCI Programming Model8-14 DSP56301 User’s Manual9TE0Transmitter EnableWhen TE is set, the transmitter is enabled. When TE is cleared, the transmitter

SCI Programming ModelSerial Communication Interface (SCI) 8-156RWU0Receiver Wakeup EnableWhen RWU is set and the SCI is in Asynchronous mode, the wake

SCI Programming Model8-16 DSP56301 User’s Manual2–0 WDS[2–0] 0 Word SelectSelect the format of transmitted and received data. Asynchronous modes are c

SCI Programming ModelSerial Communication Interface (SCI) 8-178.6.2 SCI Status Register (SSR)The SSR is a read-only register that indicates the status

SCI Programming Model8-18 DSP56301 User’s Manual4OR0Overrun Error Flag Set when a byte is ready to be transferred from the receive shift register to t

SCI Programming ModelSerial Communication Interface (SCI) 8-198.6.3 SCI Clock Control Register (SCCR)The SCCR is a read/write register that controls t

SCI Programming Model8-20 DSP56301 User’s ManualThe SCI clock determines the data transmission (baud) rate and can also establish a periodic interrupt

SCI Programming ModelSerial Communication Interface (SCI) 8-21As noted in Section 8.6.1, the SCI can be configured to operate in a single Synchronous

SCI Programming Model8-22 DSP56301 User’s Manual8.6.4 SCI Data RegistersThe SCI data registers are divided into two groups: receive and transmit, as s

SCI Programming ModelSerial Communication Interface (SCI) 8-23the data bus are read as zeros. Similarly, when SRXM is read, the contents of SRX are pl

Internal Buses1-10 DSP56301 User’s Manual1.4.6 On-Chip Memory The memory space of the DSP56300 core is partitioned into program, X data, and Y data me

GPIO Signals and Registers8-24 DSP56301 User’s Manualprevent overruns unless transmit interrupts are enabled. Either STX or STXA is usually written as

GPIO Signals and RegistersSerial Communication Interface (SCI) 8-258.7.2 Port E Direction Register (PRRE)The read/write PRRE controls the direction of

GPIO Signals and Registers8-26 DSP56301 User’s Manual

Triple Timer Module 9-1Chapter 9Triple Timer ModuleThe timers in the DSP56301 internal triple timer module act as timed pulse generators or as pulse-w

Overview9-2 DSP56301 User’s Manual9.1.1 Triple Timer Module Block DiagramFigure 9-1 shows a block diagram of the triple timer module. This module incl

OperationTriple Timer Module 9-3The timer mode is controlled by the TC[3–0] bits which are TCSR[7–4]. For a listing of the timer modes and description

Operation9-4 DSP56301 User’s Manual9.2.2 Timer InitializationTo initialize a timer, do the following:1. Ensure that the timer is not active either by

Operating ModesTriple Timer Module 9-52. Configure the interrupt trigger:a. Enable and prioritize overall peripheral interrupt functionality.IPRP (TOL

Operating Modes9-6 DSP56301 User’s Manual9.3.1 Triple Timer ModesFor all triple timer modes, the following points are true:n The TCSR[TE] bit is set t

Operating ModesTriple Timer Module 9-7Figure 9-3. Timer Mode (TRM = 1)Figure 9-4. Timer Mode (TRM = 0)Mode 0 (internal clock, no timer output): TRM =

DMAOverview 1-11The block diagram in Figure 1-1 illustrates these buses among other components.1.6 DMAThe DMA block has the following features:n Six D

Operating Modes9-8 DSP56301 User’s Manual9.3.1.2 Timer Pulse (Mode 1)In Mode 1, the timer generates an external pulse on its TIO signal when the timer

Operating ModesTriple Timer Module 9-9Figure 9-6. Pulse Mode (TRM = 0)Mode 1 (internal clock): TRM = 0N = write preloadM = write compareTE(CLK/2 or pr

Operating Modes9-10 DSP56301 User’s Manual9.3.1.3 Timer Toggle (Mode 2)In Mode 2, the timer periodically toggles the polarity of the TIO signal. When

Operating ModesTriple Timer Module 9-11Figure 9-8. Toggle Mode, TRM = 0Mode 2 (internal clock): TRM = 0N = write preloadM = write compareTETLRTCPRTCF

Operating Modes9-12 DSP56301 User’s Manual9.3.1.4 Timer Event Counter (Mode 3)In Mode 3, the timer counts external events and issues an interrupt (if

Operating ModesTriple Timer Module 9-13Figure 9-10. Event Counter Mode, TRM = 0Mode 3 (internal clock): TRM = 0N = write preloadM = write compareTE(TI

Operating Modes9-14 DSP56301 User’s Manual9.3.2 Signal Measurement ModesThe following signal measurement and pulse width modulation modes are provided

Operating ModesTriple Timer Module 9-15Figure 9-11. Pulse Width Measurement Mode, TRM = 1Figure 9-12. Pulse Width Measurement Mode, TRM = 0Mode 4 (int

Operating Modes9-16 DSP56301 User’s Manual9.3.2.2 Measurement Input Period (Mode 5)In Mode 5, the timer counts the period between the reception of sig

Operating ModesTriple Timer Module 9-17Figure 9-14. Period Measurement Mode, TRM = 0Mode 5 (internal clock): TRM = 0N = write preloadM = write compare

Peripherals1-12 DSP56301 User’s Manual1.7 PeripheralsIn addition to the core features, the DSP56301 provides the following peripherals:n As many as 42

Operating Modes9-18 DSP56301 User’s Manual9.3.2.3 Measurement Capture (Mode 6)In Mode 6, the timer counts the number of clocks that elapse between whe

Operating ModesTriple Timer Module 9-199.3.3 Pulse Width Modulation (PWM, Mode 7)In Mode 7, the timer generates periodic pulses of a preset width. Whe

Operating Modes9-20 DSP56301 User’s ManualFigure 9-16. Pulse Width Modulation Toggle Mode, TRM = 1Mode 7 (internal clock): TRM = 1N = write preloadM =

Operating ModesTriple Timer Module 9-21Figure 9-17. Pulse Width Modulation Toggle Mode, TRM = 0Mode 7 (internal clock): TRM = 0N = write preloadM = wr

Operating Modes9-22 DSP56301 User’s Manual9.3.4 Watchdog ModesThe following watchdog timer modes are provided:n Watchdog Pulsen Watchdog Toggle9.3.4.1

Operating ModesTriple Timer Module 9-23Figure 9-18. Watchdog Pulse ModeMode 9 (internal clock): TRM = 0N = write preloadM = write compareTEClock(CLK/2

Operating Modes9-24 DSP56301 User’s Manual9.3.4.2 Watchdog Toggle (Mode 10)In Mode 10, the timer toggles an external signal after a preset period. The

Triple Timer Module Programming ModelTriple Timer Module 9-259.3.4.3 Reserved ModesModes 8, 11, 12, 13, 14, and 15 are reserved.9.3.5 Special CasesThe

Triple Timer Module Programming Model9-26 DSP56301 User’s ManualFigure 9-20. Timer Module Programmer’s ModelDO DI DIR1514 13 12 11 10 9 8TC1 TC0INVTCI

Triple Timer Module Programming ModelTriple Timer Module 9-279.4.2 Timer Prescaler Load Register (TPLR)The TPLR is a read/write register that controls

PeripheralsOverview 1-131.7.4 Serial Communications Interface (SCI)The SCI provides a full-duplex port for serial communications with other DSPs, micr

Triple Timer Module Programming Model9-28 DSP56301 User’s Manual9.4.3 Timer Prescaler Count Register (TPCR)The TPCR is a read-only register that refle

Triple Timer Module Programming ModelTriple Timer Module 9-2921 TCF 0 Timer Compare FlagIndicate that the event count is complete. In timer, PWM, and

Triple Timer Module Programming Model9-30 DSP56301 User’s Manual11 DIR 0 DirectionDetermines the behavior of the TIO signal when it functions as a GPI

Triple Timer Module Programming ModelTriple Timer Module 9-317–4 TC[3–0] 0 Timer ControlControl the source of the timer clock, the behavior of the TIO

Triple Timer Module Programming Model9-32 DSP56301 User’s Manual2TCIE0Timer Compare Interrupt Enable Enables/disables the timer compare interrupts. Wh

Triple Timer Module Programming ModelTriple Timer Module 9-339.4.5 Timer Load Register (TLR)The TLR is a 24-bit write-only register. In all modes, the

Triple Timer Module Programming Model9-34 DSP56301 User’s Manual9.4.6 Timer Compare Register (TCPR)The TCPR is a 24-bit read/write register that conta

DSP56301 User’s Manual A-1Appendix ABootstrap ProgramThis appendix lists the bootstrap program for the DSP56301. ; BOOTSTRAP CODE FOR DSP56301 - (C) C

A-2 DSP56301 User’s Manual; 7-0). The memory is selected by the Address Attribute AA1 and is; accessed with 31 wait states.;; The EPROM bo

DSP56301 User’s Manual A-3; Host boot program verify that the HI32 is operational by reading; the status register (HSTR) and confirming that its va

123578ABOverviewSignals/ConnectionsMemory ConfigurationProgramming the PeripheralsEnhanced Synchronous Serial Interface (ESSI)Serial Communications In

Related Documents and Web Sites1-14 DSP56301 User’s Manual1.8 Related Documents and Web SitesThe documents listed in Table 1-3 are required for a comp

A-4 DSP56301 User’s Manual; correspondingly drive the 24-bit data mapped into the 32-bit PCI bus word.;; Note that for the synchronization purposes

DSP56301 User’s Manual A-5; HA[10] <- SBHE_ ; selects HI32 (base address 10011111); HA[9] <- SA[0] ; selects HI32 (

A-6 DSP56301 User’s Manual;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; If MD:MC:MB:MA=0100, then it loads the progra

DSP56301 User’s Manual A-7M_SCTE EQU 9 ; SCI Transmitter EnableM_TDRE EQU 1 ; Transmit Data Register EmptyM_RDRF EQU 2

A-8 DSP56301 User’s Manual bra <UB1HOSTLD ; MD:MC:MB:MA=1111, UB single strobe ;===================================================

DSP56301 User’s Manual A-9; Switch to ISA mode movep X0,X:M_DCTR ; Software personal reset move #$010020,y1 ; width 16, of

A-10 DSP56301 User’s Manual movep X:M_DRXR,y0 ; Store starting address insert x1,x0,a ; concatenate next 16-bit word

DSP56301 User’s Manual A-11 bra <FINISH ; ;========================================================================; This is the

A-12 DSP56301 User’s Manual do #6,_LOOP9 ; read number of words and starting address movem p:(r2)+,a2 ; Get the 8 LSB

DSP56301 User’s Manual A-13 rep n0 mac x0,x1,a x,l:(r0)+ ;; exercise mac, write x/y ram else

Signals/Connections 2-1Chapter 2Signals/Connections The DSP56301 input and output signals are organized into functional groups, as shown in Table 2-1.

A-14 DSP56301 User’s Manual ;; check pram clr a #start_pram,r2 ;; restore pointer, clear a do

DSP56301 User’s Manual A-15 bset #M_BAAP,x:M_AAR1 ; change AA1 polarity, in order to set ; it high; (5) ACTIVATE SERIAL INTERF

A-16 DSP56301 User’s Manual

Programming Reference B-1Chapter BProgramming ReferenceThis reference for programmers includes a table showing the addresses of all DSP memory-mapped

B-2 DSP56301 User’s ManualTable B-1. Guide to Programming SheetsModule Programming Sheet PageCentral Processor Figure B-1, Status Register (SR)page B-

Internal I/O Memory MapProgramming Reference B-3B.1 Internal I/O Memory MapTable B-2. Internal I/O Memory Map (X Data Memory) Peripheral 16-Bit Addres

Internal I/O Memory MapB-4 DSP56301 User’s ManualDMA2 $FFE7 $FFFFE7 DMA Source Address Register (DSR2)$FFE6 $FFFFE6 DMA Destination Address Register (

Internal I/O Memory MapProgramming Reference B-5HI32 $FFCD $FFFFCD DSP Slave Transmit Data FIFO (DTXS)$FFCC $FFFFCC DSP Master Transmit DATA FIFO (DTX

Internal I/O Memory MapB-6 DSP56301 User’s ManualESSI 0 $FFBC $FFFFBC ESSI 0 Transmit Data Register 0 (TX00)$FFBB $FFFFBB ESSI 0 Transmit Data Registe

Internal I/O Memory MapProgramming Reference B-7ESSI 1 $FFAC $FFFFAC ESSI 1 Transmit Data Register 0 (TX10)$FFAB $FFFFAB ESSI 1 Transmit Data Registe

2-2 DSP56301 User’s ManualFigure 2-1. Signals Identified by Functional GroupDSP563012424ExternalAddress BusExternalData BusExternalBusControlExtended

Internal I/O Memory MapB-8 DSP56301 User’s Manual$FF92 $FFFF92 Reserved$FF91 $FFFF91 Reserved$FF90 $FFFF90 ReservedTriple Timer $FF8F $FFFF8F Timer 0

Interrupt Sources and PrioritiesProgramming Reference B-9B.2 Interrupt Sources and PrioritiesTable B-3. Interrupt Sources InterruptStarting AddressInt

Interrupt Sources and PrioritiesB-10 DSP56301 User’s ManualVBA:$3E 0–2 Reserved VBA:$40 0–2 ESSI1 receive dataVBA:$42 0–2 ESSI1 receive data with exce

Interrupt Sources and PrioritiesProgramming Reference B-11Table B-4. Interrupt Source Priorities Within an IPL Priority Interrupt SourceLevel 3 (nonma

Interrupt Sources and PrioritiesB-12 DSP56301 User’s ManualESSI0 receive last slot interruptESSI0 TX data with exception interruptESSI0 transmit last

Programming SheetsProgramming Reference B-13B.3 Programming SheetsFigure B-1. Status Register (SR)Application:Date:Programmer:Sheet 1 of 2Central Proc

Programming SheetsB-14 DSP56301 User’s ManualFigure B-2. Operating Mode Register (OMR)Chip Operating ModesMOD(D:A) Mode Reset Vector Description000000

Programming SheetsProgramming Reference B-15Figure B-3. Interrupt Priority Register Core (IPRC)Application:Date:Programmer:Sheet 1 of 2 Interrupt Prio

Programming SheetsB-16 DSP56301 User’s ManualFigure B-4. Interrupt Priority Register Peripherals (IPRP)Application:Date:Programmer:Sheet 2 of 2 Interr

Programming SheetsProgramming Reference B-17Figure B-5. Phase-Locked Loop Control Register (PCTL)Application:Date:Programmer:Sheet 1 of 1PLL15 14 13 1

Signals/Connections 2-3Figure 2-2. Host Interface/Port B Detail Signal DiagramDSP56301HAD0HAD1HAD2HAD3HAD4HAD5HAD6HAD7HAD8HAD9HAD10HAD11HAD12HAD13HAD1

Programming SheetsB-18 DSP56301 User’s ManualFigure B-6. Bus Control Register (BCR)Bus Interface UnitBus Control Register (BCR)Reset = $1FFFFFBus Stat

Programming SheetsProgramming Reference B-19Figure B-7. DRAM Control Register (DCR)Bus Interface UnitDRAM Control Register (DCR)Reset = $000000Refresh

Programming SheetsB-20 DSP56301 User’s ManualFigure B-8. Address Attribute Registers (AAR[3–0])Bus Interface UnitAddress Attribute Registers 3 (AAR3)R

Programming SheetsProgramming Reference B-21Figure B-9. DMA Control Registers 5–0 (DCR[5–0])DMA Control Registers (DCR5–DCR0)Reset = $0000001514131211

Programming SheetsB-22 DSP56301 User’s ManualFigure B-10. DSP Control Register (DCTR)Host Processor (HI32)DSP Control Register (DCTR)Reset = $00000015

Programming SheetsProgramming Reference B-23Figure B-11. DSP PCI Control Register (DPCR)Host Processor (HI32)DSP PCI Control Register (DPCR)Reset = $0

Programming SheetsB-24 DSP56301 User’s ManualFigure B-12. DSP PCI Master Control Register (DPMC)Host Processor (HI32)DSP PCI Master Control Register (

Programming SheetsProgramming Reference B-25Figure B-13. DSP PCI Address Register (DPAR)DSP PCI Address Register (DPAR)Reset = $0000001514131211109876

Programming SheetsB-26 DSP56301 User’s ManualFigure B-14. HI32 Control Register (HCTR)Host Processor (HI32)HI32 Control Register (HCTR)Reset = $000000

Programming SheetsProgramming Reference B-27Figure B-15. Host Command Vector Register (HCVR)Host Processor (HI32)HI32 Command Vector Register (HCVR)Re

Power2-4 DSP56301 User’s Manual2.1 Power2.2 GroundTable 2-2. Power InputsPower NameDescriptionVCCPPLL Power—VCC dedicated for PLL use. The voltage sho

Programming SheetsB-28 DSP56301 User’s ManualFigure B-16. Status/Command Configuration Register (CSTR/CCMR)Host Processor (HI32)HI32 Status/Command Co

Programming SheetsProgramming Reference B-29Figure B-17. Header Type/Latency Timer Configuration Register (CHTY/CLAT/CCLS)Host Processor (HI32)HI32 He

Programming SheetsB-30 DSP56301 User’s ManualFigure B-18. Memory Space Base Address Configuration Register (CBMA)Host Processor (HI32)HI32 Memory Spac

Programming SheetsProgramming Reference B-31Figure B-19. Subsystem ID and Subsystem Vendor ID Configuration Register (CSID)HI32 Subsystem ID and Subsy

Programming SheetsB-32 DSP56301 User’s ManualFigure B-20. ESSI Control Register A (CRA)Application:Date:Programmer:Sheet 1 of 3ESSI1514131211109876543

Programming SheetsProgramming Reference B-33Figure B-21. ESSI Control Register B (CRB)Application:Date:Programmer:Sheet 2 of 3ESSI15 14 13 12 11 10 9

Programming SheetsB-34 DSP56301 User’s ManualFigure B-22. ESSI Transmit and Receive Slot Mask Registers (TSM, RSM)Application:Date:Programmer:Sheet 3

Programming SheetsProgramming Reference B-35Figure B-23. SCI Control Register (SCR)Application:Date:Programmer:Sheet 1 of 2SCISCI Control Register (SC

Programming SheetsB-36 DSP56301 User’s ManualFigure B-24. SCI Clock Control Registers (SCCR)Application:Date:Programmer:Sheet 2 of 2SCISCI Clock Contr

Programming SheetsProgramming Reference B-37Figure B-25. Timer Prescaler Load Register (TPLR)Application:Date:Programmer:Sheet 1 of 3Timers15 14 13 12

ClockSignals/Connections 2-52.3 Clock2.4 PLLTable 2-4. Clock SignalsSignal NameTypeState During ResetSignal DescriptionEXTAL Input Input External Cloc

Programming SheetsB-38 DSP56301 User’s ManualFigure B-26. Timer Control/Status Register (TCSR)Application:Date:Programmer:Sheet 2 of 31514131211109876

Programming SheetsProgramming Reference B-39Figure B-27. Timer Load Registers (TLR)Application:Date:Programmer:Sheet 3 of 3Timers15 14 13 12 11 10 9 8

Programming SheetsB-40 DSP56301 User’s ManualFigure B-28. Host Data Direction and Host Data Registers (HDDR, HDR)Application:Date:Programmer:Sheet 1 o

Programming SheetsProgramming Reference B-41Figure B-29. Port C Registers (PCRC, PRRC, PDRC)Application:Date:Programmer:Sheet 2 of 4GPIO236543210PCC5

Programming SheetsB-42 DSP56301 User’s ManualFigure B-30. Port D Registers (PCRD, PRRD, PDRD)Application:Date:Programmer:Sheet 3 of 4GPIOPort D (ESSI1

Programming SheetsProgramming Reference B-43Figure B-31. Port E Registers (PCRE, PRRE, PDRE)Application:Date:Programmer:Sheet 4 of 4GPIOPort E (SCI)*=

Programming SheetsB-44 DSP56301 User’s Manual

IndexDSP56301 User’s Manual Index-1Aaddermodulo 1-7offset 1-7reverse-carry 1-7Address Arithmetic Logic Unit (Address ALU) 1-7Address Attribute 0–3 (AA

Index-2 DSP56301 User’s ManualBus Row Out-of-Page Wait States (BRW) bit 4-26Bus Software Triggered Reset (BSTR) bit 4-25Bus Strobe (BS)2-7Bus X Data M

Index-3Debug modeentering 2-29external indication 2-29Debug support 1-5Detected Parity Error (DPE) bit 6-65Device/Vendor ID Configuration Register (

External Memory Expansion Port (Port A)2-6 DSP56301 User’s Manual2.5 External Memory Expansion Port (Port A) When the DSP56301 enters a low-power stan

Index-4 DSP56301 User’s ManualPCI Host Data Transfer Complete (HDTC) 6-39PCI Master Abort (MAB) 6-40PCI Master Address Request (MARQ) 6-40PCI Master R

Index-5network enhancements 7-2Network mode 7-2, 7-8, 7-10, 7-21Normal mode 7-2, 7-10, 7-20, 7-21On-Demand mode 7-10, 7-15, 7-20, 7-21operating mode

Index-6 DSP56301 User’s ManualGGeneral-Purpose Input/Output (GPIO) 1-5, 1-6, 2-2, 5-4data register 6-43direction register 6-43ESSI0 5-6ESSI1 5-6HI08 5

Index-7DSP PCI Transaction Address (High) (AR[31–16])6-32PCI Data Burst Length (BL[5–0])6-32DSP PCI Port Control Register (DPCR)6-26Clear Transmitte

Index-8 DSP56301 User’s Manualinitializing configuration registers 6-4input and output data transfers 6-4interrupt 6-22Interrupt Line-Interrupt Pin Co

Index-9II/O spaceX data memory 3-4Y data memory 3-5Idle Line Flag (IDLE) bit 8-18Idle Line Interrupt Enable (ILIE) bit 8-13Idle Line Wakeup mode 8-3

Index-10 DSP56301 User’s ManualMemory Base Address Low (PM[15–4])6-71Memory Space (MS[1–0])6-71Memory Space Indicator (MSI)6-71Pre-Fetch (PF)6-71Unive

Index-11PCI-only registersDSP PCI Address Register (DPAR) 6-33DSP PCI Master Control Register (DPMC) 6-30DSP PCI Port Control Register (DPCR) 6-26DS

Index-12 DSP56301 User’s ManualReceive Slot Mask Registers (RSMA and RSMB) 7-14, 7-35Receive with Exception Interrupt Enable (REIE) bit 8-12Received B

Index-13Asynchronous 8-1Synchronous 8-1programming model 8-9data registers 8-22Receive Data (RXD) 8-4recover synchronization 8-2reset 8-5RXD, TXD, S

External Memory Expansion Port (Port A)Signals/Connections 2-7RD Output Tri-stated Read—When the DSP is the bus master, RD is an active-low output tha

Index-14 DSP56301 User’s ManualZero (Z) 4-11Extended Mode Register (EMR) 4-7Arithmetic Saturation Mode (SM) 4-7Cache Enable (CE) 4-8Core Priority (CP)

Index-15Timer Overflow Interrupt Enable (TOIE) 9-32Timer Reload Mode (TRM) 9-30Timer Count Register (TCR) 9-34Timer Load Registers (TLR) 9-33Timer P

Index-16 DSP56301 User’s ManualX I/O memory space 3-4, 5-2X Memory Address Bus (XAB) 1-10X Memory Data Bus (XDB) 1-10X Memory Expansion Bus 1-10X-data

External Memory Expansion Port (Port A)2-8 DSP56301 User’s ManualBG Input Ignored Input Bus Grant—Asserted/deasserted synchronous to CLKOUT for proper

Interrupt and Mode ControlSignals/Connections 2-92.6 Interrupt and Mode ControlThe interrupt and mode control signals select the chip’s operating mode

123578ABOverviewSignals/ConnectionsMemory ConfigurationProgramming the PeripheralsEnhanced Synchronous Serial Interface (ESSI)Serial Communications In

Host Interface (HI32)2-10 DSP56301 User’s Manual2.7 Host Interface (HI32)The Host Interface (HI32) provides a fast parallel data port up to 32 bits wi

Host Interface (HI32)Signals/Connections 2-11HC0–HC3/HBE[3–0]HA[2–0]PB[19–16]Input/OutputInputInput or OutputTri-stated Command 0–3/Byte Enable 0–3—Wh

Host Interface (HI32)2-12 DSP56301 User’s ManualHLOCKHBSPB23Input/OutputInputInput or OutputTri-stated Host Lock—When the HI32 is programmed to interf

Host Interface (HI32)Signals/Connections 2-13HSERRHIRQOutput, open drainOutput, open drainTri-stated Host System Error—When the HI32 is programmed to

Host Interface (HI32)2-14 DSP56301 User’s ManualHAD[31–16]HD[23–8]Input/OutputInput/OutputTri-stated Host Address/Data 16–31—When the HI32 is programm

Host Interface (HI32)Signals/Connections 2-15HP8 HAD8 HD0 HIO8HP9 HAD9 HD1 HIO9HP10 HAD10 HD2 HIO10HP11 HAD11 HD3 HIO11HP12 HAD12 HD4 HIO12HP13 HAD13

Host Interface (HI32)2-16 DSP56301 User’s ManualHP40 HAD23 (pull up or down if not used)1HD15 disconnectedHP41 HAD24 (pull up or down if not used)1HD1

Host Interface (HI32)Signals/Connections 2-17HP[18–16] HC3/HBE3–HC0/HBE0 Bus Command/Byte EnableTri-state bidirectional bus.During the address phase o

Host Interface (HI32)2-18 DSP56301 User’s ManualHP22 HDEVSELHost Device SelectSustained tri-state bidirectional pin.2When actively driven, indicates t

Host Interface (HI32)Signals/Connections 2-19HP27 HREQ Bus RequestTri-state, Output pin.Indicates to the arbiter that the HI32 requires use of the bus

Contents vContentsChapter 1 Overview1.1 Manual Organization ...

Host Interface (HI32)2-20 DSP56301 User’s ManualHP29 HSTOP Host StopSustained tri-state bidirectional pin.2 Indicates that the current target is reque

Host Interface (HI32)Signals/Connections 2-21HP32 HCLKHost Bus ClockInput pin.Provides timing for all transactions on PCI. All other PCI signals are s

Enhanced Synchronous Serial Interface 02-22 DSP56301 User’s Manual2.8 Enhanced Synchronous Serial Interface 0Two synchronous serial interfaces (ESSI0

Enhanced Synchronous Serial Interface 0Signals/Connections 2-23Table 2-13. Enhanced Synchronous Serial Interface 0Signal Name TypeState During ResetSi

Enhanced Synchronous Serial Interface 02-24 DSP56301 User’s ManualSCK0PC3Input/OutputInput or OutputInput Serial Clock—Provides the serial bit rate cl

Enhanced Synchronous Serial Interface 1Signals/Connections 2-252.9 Enhanced Synchronous Serial Interface 1Table 2-14. Enhanced Serial Synchronous Inte

Enhanced Synchronous Serial Interface 12-26 DSP56301 User’s ManualSCK1PD3Input/OutputInput or OutputInput Serial Clock—Provides the serial bit rate cl

Serial Communications Interface (SCI)Signals/Connections 2-272.10 Serial Communications Interface (SCI)The SCI provides a full duplex port for serial

Timers2-28 DSP56301 User’s ManualTable 2-16. Triple Timer SignalsSignal Name TypeState During ResetSignal DescriptionTIO0 Input or Output Input Timer

JTAG and OnCE InterfaceSignals/Connections 2-292.12 JTAG and OnCE InterfaceThe DSP56300 family and in particular the DSP56301 support circuit-board te

vi DSP56303 DSP56301 User’s Manual2.8 Enhanced Synchronous Serial Interface 0 ...

JTAG and OnCE Interface2-30 DSP56301 User’s Manual

Memory Configuration 3-1Chapter 3Memory ConfigurationLike all members of the DSP56300 core family, the DSP56301 addresses three sets of 16 M × 24-bit

Program Memory Space3-2 DSP56301 User’s Manual3.1.1 Internal Program Memory The default on-chip program memory consists of a 24-bit-wide, high-speed,

X Data Memory SpaceMemory Configuration 3-33.1.4 Program Bootstrap ROMIn the current version of the DSP56301, the program memory space occupying locat

Y Data Memory Space3-4 DSP56301 User’s Manual3.2.3 Internal I/O Space—X Data MemoryOne part of the on-chip peripheral registers and some of the DSP563

Dynamic Memory Configuration SwitchingMemory Configuration 3-53.3.3 External I/O Space—Y Data MemoryThe off-chip peripheral registers should be mapped

Sixteen-Bit Compatibility Mode Configuration3-6 DSP56301 User’s Manual3.5 Sixteen-Bit Compatibility Mode ConfigurationThe sixteen-bit compatibility (S

Memory MapsMemory Configuration 3-73.7 Memory MapsThe figures in this section show the memory space and RAM configurations defined by the settings of

Memory Maps3-8 DSP56301 User’s ManualFigure 3-2. 16-Bit Space With Default RAM (0, 0, 1)Program$FFFF$0000InternalExternalX Data$FFFF$0000$0800External

Memory MapsMemory Configuration 3-9Figure 3-3. Switched Program RAM (0, 1, 0)Program$FFFFFF$000000InternalExternalX Data$FFFFFF$000000$000C00ExternalI

Contents vii4.9 JTAG Identification (ID) Register... 4-354.10 JTAG

Memory Maps3-10 DSP56301 User’s ManualFigure 3-4. 16-Bit Space With Switched Program RAM (0, 1, 1)Program$FFFF$0000InternalExternalX Data$FFFF$0000$0C

Memory MapsMemory Configuration 3-11Figure 3-5. Instruction Cache Enabled (1, 0, 0)Program$FFFFFF$000000InternalExternalX Data$FFFFFF$000000$000800Ext

Memory Maps3-12 DSP56301 User’s ManualFigure 3-6. 16-Bit Space With Instruction Cache Enabled (1, 0, 1)Program$FFFF$0000InternalExternalX Data$FFFF$00

Memory MapsMemory Configuration 3-13Figure 3-7. Switched Program RAM and Instruction Cache Enabled (1, 1, 0)Program$FFFFFF$000000InternalExternalX Dat

Memory Maps3-14 DSP56301 User’s ManualFigure 3-8. 16-Bit Space, Switched Program RAM, Instruction Cache Enabled (1, 1, 1)Program$FFFF$0000InternalExte

Core Configuration 4-1Chapter 4Core ConfigurationThis chapter presents DSP56300 core configuration details specific to the DSP56301. These configurati

Operating Modes4-2 DSP56301 User’s Manual4.1 Operating ModesThe operating modes govern not only how the DSP56301 operates but also the start-up proced

Operating ModesCore Configuration 4-3Table 4-2. Operating Mode DefinitionsMode Description0 Expanded mode—Bypasses the bootstrap ROM. The DSP56301 beg

Operating Modes4-4 DSP56301 User’s Manual6 Host bootstrap 8-bit wide UB mode in double-strobe pin configuration—The hardware reset vector is located a

Bootstrap ProgramCore Configuration 4-54.2 Bootstrap ProgramIn recent revisions of the DSP56301, the bootstrap program is factory-programmed in an int

viii DSP56303 DSP56301 User’s Manual6.7.10 DSP Host Port GPIO Direction Register (DIRH)...

Central Processor Unit (CPU) Registers4-6 DSP56301 User’s ManualYou can invoke the bootstrap program options (except modes 0 and 8) at any time by set

Central Processor Unit (CPU) RegistersCore Configuration 4-7n Condition Code Register (CCR) (SR[7–0])—Defines the results of previous arithmetic compu

Central Processor Unit (CPU) Registers4-8 DSP56301 User’s Manual20 SM 0 Arithmetic Saturation ModeSelects automatic saturation on 48 bits for the resu

Central Processor Unit (CPU) RegistersCore Configuration 4-914 DM 0 Double-Precision Multiply ModeEnables four multiply/MAC operations to implement a

Central Processor Unit (CPU) Registers4-10 DSP56301 User’s Manual11–10 S[1–0] 0 Scaling ModeSpecify the scaling to be performed in the Data ALU shifte

Central Processor Unit (CPU) RegistersCore Configuration 4-116L0LimitSet if the overflow bit is set or if the data shifter/limiter circuits perform a

Central Processor Unit (CPU) Registers4-12 DSP56301 User’s Manual4.3.2 Operating Mode Register (OMR)The OMR is a read/write register divided into thre

Central Processor Unit (CPU) RegistersCore Configuration 4-1318 EOV 0 Stack Extension Overflow FlagSet when a stack overflow occurs in Stack Extended

Central Processor Unit (CPU) Registers4-14 DSP56301 User’s Manual12 BRT 0 Bus Release Timing Selects between fast or slow bus release. If BRT is clear

Configuring InterruptsCore Configuration 4-154.4 Configuring InterruptsDSP56301 interrupt handling, like that for all DSP56300 family members, is opti

Contents ix7.5.1 ESSI Control Register A (CRA)... 7-147.5.2 ESS

Configuring Interrupts4-16 DSP56301 User’s Manual4.4.1 Interrupt Priority Registers (IPRC and IPRP)There are two interrupt priority registers in the D

Configuring InterruptsCore Configuration 4-17The DSP56301 has a four-level interrupt priority structure. Each interrupt has two interrupt priority lev

Configuring Interrupts4-18 DSP56301 User’s ManualVBA:$10 0–2 IRQAVBA:$12 0–2 IRQBVBA:$14 0–2 IRQCVBA:$16 0–2 IRQDVBA:$18 0–2 DMA channel 0VBA:$1A 0–2

Configuring InterruptsCore Configuration 4-194.4.3 Processing Interrupt Source Priorities Within an IPLIf more than one interrupt request is pending w

Configuring Interrupts4-20 DSP56301 User’s ManualIRQC (external interrupt)IRQD (external interrupt)DMA channel 0 interruptDMA channel 1 interruptDMA c

PLL Control Register (PCTL)Core Configuration 4-214.5 PLL Control Register (PCTL)The bootstrap program must initialize the system Phase-Lock Loop (PLL

Bus Interface Unit (BIU) Registers4-22 DSP56301 User’s Manual4.6 Bus Interface Unit (BIU) RegistersThe three Bus Interface Unit (BIU) registers config

Bus Interface Unit (BIU) RegistersCore Configuration 4-2320–16 BDFW[4–0] 11111(31 wait states)Bus Default Area Wait State ControlDefines the number of

Bus Interface Unit (BIU) Registers4-24 DSP56301 User’s Manual4.6.2 DRAM Control Register (DCR)The DRAM controller is an efficient interface to dynamic

Bus Interface Unit (BIU) RegistersCore Configuration 4-25Table 4-10. DRAM Control Register (DCR) Bit DefinitionsBit NumberBit NameReset ValueDescripti