Motorola MPC5200 Manual de usuario descargar pdf (Pagina 2)

MPC5200 Microprocessor Technical Summary, Rev. 3

Key Features

Freescale Semiconductor2

With the success of the MPC5200 in the automotive market, other markets can now enjoy extended

automotive temperature qualification and life cycles typically found in that industry. The MPC5200 is

engineered to support an external dual-bus architecture with a separate high-speed SDRAM/DDR

controller used primarily by the PowerPC processor core. A Peripheral Component Interconnect (PCI)

compatible interface may be used as a generalized interface to system level peripherals in addition to the

ATA/IDE interface which provides access to disk drives.

1 Key Features

MPC603e series PowerPC core

• Superscalar architecture

• 0 – 400 MHz static operation MPC5200CBV400

(-40°C to +85°C temperature range)

• 0 – 400 MHz static operation MPC5200BV400

(0°C to +70°C temperature range)

• 16 K Instruction / 16 K Data Caches

• Double-precision FPU

• Instruction and Data MMU

• Dynamic power management including Doze and Sleep modes

• 159 microseconds to first instruction execution at power-on at 400 MHz

• Standard & critical interrupt capability

High speed SDRAM memory interface

• 133 MHz operation (266 MHz effective with DDR)

• SDR & DDR SDRAM support

• 256 Mbyte addressing range

• 32-bit data bus

• Built-in initialization and refresh

Flexible multi-function external bus

• Supports PCI, ATA/IDE, and ROM/RAM/Flash interfaces

• Version 2.2 PCI master compatibility

— 32-bit multiplexed address/data

— 66 MHz operation with BestComm enabled

• Version 4 ATA compatible external interface

• IDE Disk Drive connectivity

• ROM/RAM/Flash interface

— Boot ROM, external peripheral connectivity

— Non multiplexed data access using 8/16/32 bit databus with up to 26 bit address bus

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Motorola MPC5200 Manual de usuario Pagina 2