Motorola MC68340 Especificaciones

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Application Note 073
—————————————————
Product and company names are trademarks or trade names of their respective companies.
340993B-01 © Copyright 1997 National Instruments Corporation. All rights reserved. December 1997
Using the TNT4882 in an MC68340 System
Andrew Thomson
Faisal Habib
Introduction
This application note is written for GPIB instrument designers who use the Motorola MC68340 processor. It describes
the hardware interface required to create a fully functional GPIB device using the National Instruments TNT4882
GPIB interface chip with the Motorola MC68340.
In this document we show how to create an interface that will meet the following specifications:
Complete IEEE 488.2 Talker/Listener functionality based on the TNT4882-AQ
8 and 16-bit data transfers
Polled I/O, Interrupt Driven I/O, and Direct Memory Access (DMA)
16-bit Single Address DMA transfers between RAM and TNT4882
Note that the terms assert (assertion) and negate (negation) are used to avoid confusion when dealing with a mixture
of active low and active high signals. The term assert (assertion) means that a signal is active or true, independent of
the level represented by a high or low voltage. The term negate (negation) means that a signal is inactive or false, inde-
pendent of the level represented by a high or low voltage.
Source files for the test program are included in the Appendix. Before you use the hardware test program, make any
changes necessary to the header files and recompile the program. We used Microtec Research Software Development
Tools, Version 4.2D for DOS and an M6834OEVS System.
Hardware Description
The TNT4882 has two different pin configurations – ISA and Generic. This application uses the TNT4882 in Generic
pin configuration. Refer to Chapter 5 in the TNT4882 Programmer Reference Manual for a Generic pin description.
Figure 1 shows the MC68340 and TNT4882 hardware interface diagram. The interface logic can be implemented
easily in a Programmable Array Logic (PAL) device such as a 16V8.
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Indice de contenidos

Pagina 1 - Hardware Description

Application Note 073—————————————————Product and company names are trademarks or trade names of their respective companies.340993B-01 © Copyright 1997

Pagina 2 - Synchronous Bus Operation

10Downloading ProceduresA Widows terminal settings file is also included on the disk. Execute the following steps to download a program:1. Start Windo

Pagina 3 - TNT4882 ABUSN, BBUSN Signals

11In the DMA I/O test routine, the channel is initialized by clearing the status register and loading the byte transfer valuein the byte counter regis

Pagina 4 - TNT4882 DMA Signals

12puts()PrintHex()RET340BUG()References1. MC68340 Integrated Processor with DMA User’s Manual, Motorola Inc., 1992.2. TNT4882 Programmer Reference Man

Pagina 5 - Asynchronous Bus Operation

13Register.H#ifndef __REGISTER_H#define __REGISTER_H #define BASE 0x00FFE800 #define DIR *(unsigned char *) (BASE + 0x00) #define CDOR *(

Pagina 6 - Other CPU Interface Pins

14 #define B_S3 (SPSR & 0x04) #define B_S4 (SPSR & 0x08) #define B_S5 (SPSR & 0x10) #define B_S6 (SPSR

Pagina 7

15 #define ClrREN 0x17 #define REQT 0x18 #define REQF 0x19 #define TCSE 0x1A #define LTNnCont 0x1B #define

Pagina 8 - Software Consideration

16 #define AUXRJ 0xF0 #define TM(value) (AUXRJ | value) #define CNT3 *(unsigned char *) (BASE + 0x2D) #define CNT2 *(unsigned ch

Pagina 9 - Hardware Interface Test

17 #define t13 0xC0 #define T13(value) (t13 | value) #define HIER *(unsigned char *) (BASE + 0x4D) #define E_PMTwEOS 0x01 #d

Pagina 10 - DMA I/O Test

18 #define B_bsrDAV (BSR & 0x40) #define B_ATN (BSR & 0x80) #define BCR *(unsigned char *) (BASE + 0x7D) #define E_REN

Pagina 11 - MC340BUG Library

19MC68340.H#ifndef __MC68340_H#define __MC68340_H#define MCBASE 0xFFFFF000/**********************System Integration Module (SIM)*********************

Pagina 12 - References

2Figure 1. MC68340 and TNT4882 Interface Hardware DiagramSynchronous Bus OperationTNT4882 Address LinesAddress lines A6-A2 of MC68340 connect directl

Pagina 13 - Register.H

20#define MR2A *(unsigned char *) (MCBASE + 0x720)#define MR1B *(unsigned char *) (MCBASE + 0x718)#define SRB *(unsigned char *) (MCBASE + 0

Pagina 14

21MC340BUG.H/*************************************************************************//* File Name : MC340BUG.H

Pagina 15

22HARDWARE.H/**************************************************************************//* File Name : HARDWARE.H

Pagina 16

23HARDWARE.C/**************************************************************************//* File Name : HARDWARE.C

Pagina 17

24 { NEWLN(); PrintHex(counter); puts("Loop"); fail |= Programmed_IO_Test(); fail |= Int

Pagina 18

25/* 1. 8 Bit accesses to FIFO A *//* 2. 8 Bit accesses to FIFO B

Pagina 19 - MC68340.H

26formed.\n\n"); return ERROR; } else { Failure = FALSE; EnableMC68340Interrupts; IMR3 = E_NFF; /*wr

Pagina 20

27/**************************************************************************//***********************************************************************

Pagina 21 - MC340BUG.H

28/* Created On : 05/23/95 *//* Modified On : 05/23/95

Pagina 22 - HARDWARE.H

29TEST4882.H/**************************************************************************//* File Name : TEST4882.H

Pagina 23 - HARDWARE.C

3TNT4882 ABUSN, BBUSN SignalsThe TNT4882 has the capability of using either of its data busses for 8-bit I/O accesses. Either Bus A (D15-8) or BusB (D

Pagina 24

30TEST4882.C/**************************************************************************//* File Name : TEST4882.C

Pagina 25

31}/**************************************************************************//**********************************************************************

Pagina 26

32 } return result;}/**************************************************************************//***************************************************

Pagina 27

33 if (StoredValue != TestBit16[Loop]) /*compare w/ values in TestBit16[]*/ { DisplayErrorMessage(StoredValue,TestBit16[Loop]); if (!(

Pagina 28

34/* the fifos. The values are read during a READ interrupt.*//***********************************************************************

Pagina 29 - TEST4882.H

35 puts(": Received Value");}/**************************************************************************//********************************

Pagina 31

4TNT4882 RDN, WRN SignalsDuring write accesses, the TNT4882 latches data on the rising edge of WRN. The TNT4882 drives its data buses whenRDN is asser

Pagina 32

5Figure 5. DMA Write (TNT4882 to Memory) Timing DiagramAsynchronous Bus OperationNormally, the TNT4882 is used in one chip mode. See Chapter 2 in the

Pagina 33

6Interrupt Acknowledge Bus OperationThe TNT4882 can interrupt the processor by asserting its interrupt signal. The MC68340 will acknowledge theinterru

Pagina 34

7MODE PinThe MODE pin determines whether the TNT4882 enters Turbo+7210 mode or Turbo+9914 mode after a hardwarereset. For the above interface, MODE wa

Pagina 35

8Software ConsiderationOnce the hardware interface has been constructed, a few initialization routines need to be performed. Once theseinitialization

Pagina 36

9Interrupt ConfigurationSince the above setup requires an autovector, we need to program the autovector register so that the vector number isgenerated

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