Motorola MCU 68HC912 Manual de usuario descargar pdf (Pagina 3)

SLAA108A

SPI-Based Data Acquisition/Monitor Using the TLC2551 Serial ADC 3

System Timing

DAC

ADC

Figure 2. System Timing Diagram

A to D Requirements

The 12-bits of serial output data from the TLC2551 are presented MSB first after the falling edge

of chip select. The ADC’s chip select pin must be held low through two SPI transfers in order to

allow the ADC to output the contents of its data register. Output data changes on the rising

edge of SCLK, and is valid on the falling. The ADC also uses this time to complete the next data

sampling cycle. For data to be released on the next chip select cycle, the ADC requires at least

one falling SCLK edge while its chip select pin is in the high state. Asserting the micros SS/CS

pin high before the completion of conversion, satisfies this requirement. Frame sync to the ADC

is held high in this application.

D to A Requirements

Output data from the ADC is stored as two 8-bit words in the microprocessor. Before the data

can be transmitted to the TLV5616 it must be formatted. Since the DAC is expecting the first

data nibble to contain configuration information, the data received from the ADC must be padded

with leading zeros by shifting the data right by four bits. Conversion speed and power down

commands can be inserted by masking the shifted data.

The DAC’s chip select is held low in this application. Toggling a general-purpose I/O pin on the

micro can generate frame Sync to the DAC. This alerts the DAC to an incoming serial data

stream. Data is presented to the DAC MSB first, in two subsequent SPI transfers from the

microcontroller. The first four bits of data contain the configuration information, while the

remaining 12-bits are data from the previous ADC conversion results.

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Motorola MCU 68HC912 Manual de usuario Pagina 3