Motorola MCU 68HC912D60 Manual de usuario descargar pdf (Pagina 10)

10 68HC912D60MSE4 Rev 2

March 14, 2001

in LHM since no crystal oscillations will be detected. This situation can arise with

short reset periods and/or crystals that exhibit slow start-up characteristics.

For the first 4096 cycles i.e. during the internal reset period, Limp Home mode will

be de-asserted if oscillator activity is detected by the clock monitor circuit -due to

the asserted Reset signal there can be no CPU activity during the Reset phase.

Following release of the external or internal POR RESET in LHM (which ever is

later) the crystal oscillator is sampled by the clock monitor circuit after another 4096

VCO clock cycles and at intervals of 8192 clock cycles thereafter until the crystal

is deemed to be operating. If the crystal oscillator is showing activity at the time it

is checked then it will be deemed to be good, even though it may not have fully

stabilized, and LHM will be de-asserted. This can cause the device to switch from

LH mode to normal mode with the CPU clocked from an unstable signal from the

crystal oscillator (see fig. 2) resulting in unpredictable function of the CPU.

The COP Reset doesn’t exhibit this behavior as, although the same reset

sequence is followed, the oscillator isn’t stopped.

When exiting Stop mode (DLY=1) a similar 4096 cycle delay is executed and

therefore this behavior could also show up at this time. In applications where this

is likely to be an issue, using pseudo-stop is recommended as an alternative.

Current draw will increase <100 ?A at 4MHz in pseudo stop versus stop mode.

Following a loss of external clock in normal operation, Limp Home mode will be

entered successfully but if the oscillator is reconnected for some reason a similar

situation may arise.

The Reset condition can be overcome by allowing the crystal oscillator circuit to

stabilize before releasing the external RESET line (see fig. 3). Operation is similar

to that shown in fig 2.

To determine if crystal is ’stable’ at the release of reset can be difficult and the time

can vary some from board to board. If the customer has special high impedance

probes, it is possible to monitor the amplitude of the voltage from XTAL to ground

(<2 pF scope probes are recommended). Please note that any loading on the

circuit can affect its operation. (Any resistance to ground or Vdd on the EXTAL pin

can greatly attenuate the amplifier gain and cause erroneous operation.)

A second way to measure the oscillator startup time is to monitor the XFC pin. This

method does not require a high impedance scope probe. The PLL will not lock until

the oscillator clock feeding it is present and stable. Remove the external reset

circuit and during power up watch the XFC pin. The voltage should start high (Vdd).

After the part releases internal reset it will drop to some stable voltage between

Vdd and Vss. If external reset (measured independent from this test) is held till this

’stable voltage’ time the oscillator will be stable. Please note the filter components

mounted on the XFC pin will affect this ramp (for evaluation purposes, alternative

components can be selected to provide a fast lock time). More than one board

should be measured because of pcb and crystal variability. It is also recommended

that the test be run over the operating temperature of the device.

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