Motorola MCU 68HC912D60 Manual de usuario descargar pdf (Pagina 4)

4 68HC912D60MSE4 Rev 2

March 14, 2001

CGM: CRYSTAL START-UP WITHOUT DELAY AT CLOCK MONITOR RESET

AR509

When a clock monitor reset occurs, the crystal may start-up with no delay period.

As a result, the MCU attempts to fetch reset vectors before the crystal has fully

stabilized.

Work-

around

When clock monitor failure has occurred, hold the reset signal until the crystal has

reached stable oscillation.

In some applications the clock monitor reset is used to detect an accidental crystal

clock loss. An alternative solution is to engage the PLL and enable the limp-home

mode. As the limp-home mode is enabled, the clock monitor will not reset the MCU

(NOLHM =0 in PLLCR). In case of clock loss, the limp-home mode will be engaged.

If the crystal clock is restored, the PLL will be automatically re-engaged. As the

transition from PLL to limp-home and vice versa is smooth, the CPU will continue

to run the code even if the crystal oscillation amplitude is not fully stabilized.

The LHIF flag in PLLFLG is set when MCU enters or exits the limp-home condition.

CGM: CANNOT INTERRUPT OUT OF STOP WITH DLY=1 AR565

STOP mode cannot be exited using interrupts when DLY=1 depending on where

the Real-Time-Interrupt (RTI) counter is when the STOP instruction is executed.

The RTI counter is free-running during normal operation and is only reset at the

beginning of Reset, during Power-on-Reset, and after entry into STOP. The

free-running counter will generate a one cycle pulse every 4096 cycles. If that pulse

occurs at the exact same time that the stop signal from the CPU is asserted then

the OSC is stopped but the internal stop signal will remain low. In this state the

OSC is shut off until RESET.

Work-

around

1. If you are not using the Real Time Interrupt function you can wait for a RTI

flag before entering into STOP to guarantee the counter is in a safe state.

When executing the following code all interrupt sources except for those

used to exit STOP mode must be masked to prevent a loss of

synchronization.

A loss of synchronization can occur if an interrupt is processed between the

setting of the RTIF and the execution of the STOP instruction. Also, you must

enable the RTI counter in the initialization code, set to the fastest RTI

time-out period, and the RTIE bit should NOT be set.

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