
MPC5200 Data Sheet, Rev. 4
Electrical and Thermal Characteristics
Freescale Semiconductor22
Table 20. DDR SDRAM Memory Read Timing
Sym Description Min Max Units SpecID
t
mem_clk
MEM_CLK period 7.5 — ns A5.15
t
valid
Control Signals, Address and MBA
valid after rising edge of MEM_CLK
—t
mem_clk
*0.5+0.4 ns A5.16
t
hold
Control Signals, Address and MBA
hold after rising edge of MEM_CLK
t
mem_clk
*0.5 — ns A5.17
t
data_sample_max
Read Data sample window — 4.59
1
NOTES:
1
Calculated with maximum number of Tap delay, 31 Tap delay are selected.
ns A5.18
t
data_sample_min
Read Data sample window 1.55
2
2
Calculated with minimum number of Tap delay, 0 Tap delay are selected.
— ns A5.19
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