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Electrical and Thermal Characteristics
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor 9
3.1.4 Electrostatic Discharge
CAUTION
This device contains circuitry that protects against damage due to
high-static voltage or electrical fields. However, it is advised that normal
precautions be taken to avoid application of any voltages higher than
maximum-rated voltages. Operational reliability is enhanced if unused
inputs are tied to an appropriate logic voltage level (i.e., either GND or
V
CC
). Table 7 gives package thermal characteristics for this device.
3.1.5 Power Dissipation
Power dissipation of the MPC5200 is caused by 3 different components: the dissipation of the internal or
core digital logic (supplied by VDD_CORE), the dissipation of the analog circuitry (supplied by
SYS_PLL_AVDD and CORE_PLL_AVDD) and the dissipation of the IO logic (supplied by
VDD_IO_MEM and VDD_IO). Table 6 details typical measured core and analog power dissipation
figures for a range of operating modes. However, the dissipation due to the switching of the IO pins can
not be given in general, but must be calculated by the user for each application case using the following
formula
DRV8_OD VDD_IO = 3.3V - 8 mA D3.27
DRV16_MEM VDD_IO_MEM = 3.3V 16 16 mA D3.28
DRV16_MEM VDD_IO_MEM = 2.5V 16 16 mA D3.29
PCI VDD_IO = 3.3V 16 16 mA D3.30
Table 5. ESD and Latch-Up Protection Characteristics
Sym Rating Min Max Unit SpecID
V
HBM
Human Body Model (HBM)—JEDEC JESD22-A114-B 2000 — V D4.1
V
MM
Machine Model (MM)—JEDEC JESD22-A115 200 — V D4.2
V
CDM
Charge Device Model (CDM)—JEDEC JESD22-C101 500 — V D4.3
I
LAT
Latch-up Current at T
A
=85
o
C
positive
negative
+100
-100
—mA
D4.4
I
LAT
Latch-up Current at T
A
=27
o
C
positive
negative
+200
-200
—mA
D4.5
Table 4. Drive Capability of MPC5200 Output Pins (continued)
Driver Type Supply Voltage I
OH
I
OL
Unit SpecID
P
IO
P
IOint
N
M
∑
+ CVDD_IO
2
f×××=
- MPC5200 Data Sheet 1
- 2Features 2
- Features 3
- Freescale Semiconductor 3 3
- • Test/Debug features 4
- Freescale Semiconductor 5 5
- (see Table 2) 7
- 3.1.4 Electrostatic Discharge 9
- 3.1.5 Power Dissipation 9
- 3.1.6 Thermal Characteristics 11
- 3.1.7 Heat Dissipation 11
- MPC5200 Data Sheet, Rev. 4 12
- Freescale Semiconductor12 12
- 3.3.2 Clock AC Specifications 15
- 3.3.3 Resets 16
- 3.3.4 External Interrupts 18
- GPIO_PSC3_5 19
- GPIO_PSC3_4 19
- 3.3.5 SDRAM 20
- Row Column 21
- 3.3.6 PCI 25
- 3.3.7 Local Plus Bus 28
- 3.3.7.2 Burst Mode 30
- 3.3.7.3 MUXed Mode 32
- 3.3.8 ATA 33
- Figure 15. PIO Mode Timing 35
- 3.3.9 Ethernet 44
- 3.3.10 USB 46
- 3.3.11 SPI 47
- 3.3.12 MSCAN 51
- 3.3.13 I 51
- 3.3.14 J1850 52
- 3.3.15 PSC 53
- 3.3.15.2 AC97 Mode 55
- 3.3.15.3 IrDA Mode 56
- 3.3.15.4 SPI Mode 57
- 3.3.16 GPIOs and Timers 61
- INPUT DATA VALID 63
- OUTPUT DATA VALID 63
- 4 Package Description 64
- CASE 1135A–01 65
- DATE 10/15/1997 65
- 4.3 Pinout Listings 66
- 5 System Design Information 71
- 5.1.1 Power Up Sequence 72
- 5.1.2 Power Down Sequence 73
- 5.4 JTAG 74
- 5.4.2 G2_LE COP/BDM Interface 75
- COP Header 77
- COP Connector 77
- Physical Pinout 77
- System Design Information 78
- Freescale Semiconductor78 78
- 6 Ordering Information 79
- 7 Document Revision History 79
- How to Reach Us: 80
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